TCI6636K2H Datasheet, PDF (325/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-44 HyperLink Peripheral Switching Characteristics (Part 2 of 2)
(see Figure 10-39, Figure 10-40 and Figure 10-41)
No.
Parameter
Min
Max
Unit
5 toh(HYPTXPMCLKH-HYPTXPMDAT) Hold time - HYPTXPMDAT valid after HYPTXPMCLK high
0.25*C2-0.4
ns
4 tosu(HYPTXPMDAT-HYPTXPMCLKL) Setup time - HYPTXPMDAT valid before HYPTXPMCLK low
0.25*C2-0.4
ns
5 toh(HYPTXPMCLKL-HYPTXPMDAT) Hold time - HYPTXPMDAT valid after HYPTXPMCLK low
0.25*C2-0.4
ns
End of Table 10-44
Figure 10-39 HyperLink Station Management Clock Timing
1
2
3
Figure 10-40 HyperLink Station Management Transmit Timing
45
HYPTX<xx>CLK
45
HYPTX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 10-41 HyperLink Station Management Receive Timing
67
HYPRX<xx>CLK
67
HYPRX<xx>DAT
<xx> represents the interface that is being used: PM or FL
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TCI6636K2H Peripheral Information and Electrical Specifications 325