TCI6636K2H Datasheet, PDF (331/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.19 Timers
The timers can be used to time events, count events, generate pulses, interrupt the CorePacs, and send
synchronization events to the EDMA3 channel controller.
10.19.1 Timers Device-Specific Information
The TCI6636K2H device has up to twenty 64-bit timers in total, of which Timer0 through Timer7 are dedicated to
each of the up to eight C66x CorePacs as watchdog timers and can also be used as general-purpose timers. Timer16
through Timer19 are dedicated to each of the Cortex-A15 processor cores as a watchdog timer and can also be used
as general-purpose timers.The remaining timers can be configured as general-purpose timers only, with each timer
programmed as a 64-bit timer or as two separate 32-bit timers.
When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period. When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up
of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to
the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that
software writes to the timer before the count expires, after which the count begins again. If the count ever
reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming ‘‘Reset
Type Status Register (RSTYPE)’’ on page 300 and the type of reset initiated can set by programming ‘‘Reset
Configuration Register (RSTCFG)’’ on page 302. For more information, see the 64-bit Timer (Timer 64) for KeyStone
Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
10.19.2 Timers Electrical Timing
The tables and figures below describe the timing requirements and switching characteristics of the timers.
Table 10-52 Timer Input Timing Requirements ⁽¹⁾
(see Figure 10-51)
No.
1
t_w(TINPH)
2
t_w(TINPL)
End of Table 10-52
Pulse duration, high
Pulse duration, low
Min
Max Unit
12C
ns
12C
ns
1 C = 1/SYSCLK clock frequency in ns
Table 10-53 Timer Output Switching Characteristics ⁽¹⁾
(see Figure 10-51)
No.
3
t_w(TOUTH)
4
t_w(TOUTL)
End of Table 10-53
Pulse duration, high
Pulse duration, low
Parameter
1 C = 1/SYSCLK1 clock frequency in ns.
Figure 10-51 Timer Timing
1
2
Min
12C - 3
12C - 3
Max Unit
ns
ns
TIMIx
3
4
TIMOx
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 331