TCI6636K2H Datasheet, PDF (347/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-61 Emulation Interface with Different Debug Port Configurations (Part 2 of 2)
Cross
EMU Pins Triggering
ARM Trace
DSP Trace
STM
EMU18
TRCDTa[14] TRCDTb[16] TRCDTa[14] TRCDTb[16] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU17
TRCDTa[13] TRCDTb[15] TRCDTa[13] TRCDTb[15] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU16
TRCDTa[12] TRCDTb[14] TRCDTa[12] TRCDTb[14] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU15
TRCDTa[11] TRCDTb[13] TRCDTa[11] TRCDTb[13] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU14
TRCDTa[10] TRCDTb[12] TRCDTa[10] TRCDTb[12] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU13
TRCDTa[9] TRCDTb[11] TRCDTa[9] TRCDTb[11] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU12
TRCDTa[8] TRCDTb[10] TRCDTa[8] TRCDTb[10] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU11
TRCDTa[7] TRCDTb[9] TRCDTa[7] TRCDTb[9] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU10
TRCDTa[6] TRCDTb[8] TRCDTa[6] TRCDTb[8] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU9
TRCDTa[5] TRCDTb[7] TRCDTa[5] TRCDTb[7] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU8
TRCDTa[4] TRCDTb[6] TRCDTa[4] TRCDTb[6] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU7
TRCDTa[3] TRCDTb[5] TRCDTa[3] TRCDTb[5] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU6
TRCDTa[2] TRCDTb[4] TRCDTa[2] TRCDTb[4] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU5
TRCDTa[1] TRCDTb[3] TRCDTa[1] TRCDTb[3] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU4
TRCDTa[0] TRCDTb[2] TRCDTa[0] TRCDTb[2] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU3
TRCCTRL
TRCCTRL
TRCCLKB
TRCCLKB
TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU2
TRCCLK
TRCCLK
TRCCLKA TRCCLKA TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU1 Trigger1
TRCDTb[1]
TRCDTb[1] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
EMU0 Trigger0
TRCDTb[0]
TRCDTb[0] TRCDT3, or TRCDT2, or TRCDT1, or TRCDT0, or
TRCCLK, or Tri-state
End of Table 10-61
Debug
Boot Mode
dbgbootmode[1]
dbgbootmode[0]
10.36.1 Concurrent Use of Debug Port
Following combinations are possible concurrently:
• Trigger 0/1
• Trigger 0/1 and STM Trace (upto 4 datapins)
• Trigger 0/1 and STM Trace (upto 4 datapins) and C66x Trace (upto 20 datapins)
• Trigger 0/1 and STM Trace (1-4 datapins) and ARM Trace (27-24 datapins)
• STM Trace (1-4 datapins) and ARM Trace (29-26 data pins)
• Trigger 0/1 and ARM Trace (upto 29 data pins)
• ARM Trace (upto 32 datapins)
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TCI6636K2H Peripheral Information and Electrical Specifications 347