TCI6636K2H Datasheet, PDF (23/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
3.1.2 L1D Memory
The L1D memory configuration for the TCI6636K2H device is as follows:
• Region 0 size is 0K bytes (disabled)
• Region 1 size is 32K bytes with no wait states
Figure 3-3 shows the available SRAM/cache configurations for L1D.
Figure 3-3 L1D Memory Configurations
L1D Mode Bits
000
001
010
011
100
L1D Memory
Block Base
Address
00F0 0000h
All
SRAM
7/8
SRAM
3/4
SRAM
1/2
SRAM
2-Way
Cache
2-Way
Cache
2-Way
Cache
2-Way
Cache
16K bytes
8K bytes
4K bytes
4K bytes
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
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