TCI6636K2H Datasheet, PDF (333/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.24 Bit Rate Coprocessor (BCP)
The BCP is a hardware accelerator for wireless infrastructure and performs most of the uplink and downlink layer 1
bit processing for 3G and 4G wireless standards. BCP supports LTE, LTE-A, FDD WCDMA, TD-SCDMA, and
WiMAX 802.16-2009 standards. It supports various downlink processing blocks like CRC attachment, turbo
encoding, rate matching, code block concatenation, scrambling, and modulation. BCP supports various uplink
processing blocks like soft slicer, de-scrambler, de-concatenation, rate de-matching, and LLR combining. For more
information, see the Bit Coprocessor (BCP) for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from
Texas Instruments’’ on page 19.
10.25 Serial RapidIO (SRIO) Port
The SRIO port on the device is a high-performance, low pin-count SerDes interconnect. SRIO interconnects in a
baseband board design provide connectivity and control among the components. The device supports four 1× Serial
RapidIO links or one 4× Serial RapidIO link. The SRIO interface is designed to operate at a data rate of up to 5 Gbps
per differential pair. This equals 20 raw GBaud/s for the 4× SRIO port, or approximately 15 Gbps data throughput
rate.
The PHY part of the SRIO consists of the physical layer and includes the input and output buffers (each serial link
consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in 2.4 ‘‘Related
Documentation from Texas Instruments’’ on page 19.
10.25.1 Serial RapidIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different from other interfaces. For these other
interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information
specification (IBIS) models.
The Serial RapidIO peripheral is a master peripheral in the device. It conforms to the RapidIO™ Interconnect
Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.
For the SRIO port, Texas Instruments provides a PCB solution showing two TI SRIO-enabled DSPs connected
together via a 4× SRIO link. TI has performed the simulation and system characterization to ensure all SRIO
interface timings in this solution are met.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
10.26 General-Purpose Input/Output (GPIO)
10.26.1 GPIO Device-Specific Information
The GPIO peripheral pins are used for general purpose input/output for the device. These pins are also used to
configure the device at boot time.
For more detailed information on device/peripheral configuration and the TCI6636K2H device pin muxing, see
‘‘Device Configuration’’ on page 233.
These GPIO pins can also used to generate individual core interrupts (no support of bank interrupt) and EDMA
events.
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TCI6636K2H Peripheral Information and Electrical Specifications 333