SH7710 Datasheet, PDF (985/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
19.3.5 Padding Insertion in
Receive data
19.3.5 Receive FIFO Overflow
Alert Signal (ARBUSY)
773 Deleted
773 The ARBUSY signal synchronized with the bus clock (B
clock) signal is also output to an external pin of this LSI.
When the capacity of data received in receive FIFO or
the number of receive frames reach the threshold
(RFF2 to RFF0, or RFD2 to RFD0) specified in FCFTR
in E-DMAC, ARBUSY is valid.
19.4 Usage Notes
776 Added
Section 24 List of Registers
816 RPADIR0 deleted
24.1 Register Addresses
(by functional module, in order of
the corresponding section
numbers)
RPADIR1 deleted
24.2 Register Bits
843
Register
Abbrevia- Bit 28/
tion
20/12/4
TRSCERn 
(n = 0, 1) _


Bit 27/
19/11/3




Bit 26/
18/10/2




Bit 25/
17/9/1




Bit 24/
16/8/0




844 RPADIRn (n = 0, 1) deleted
844
Register
Abbrevia- Bit 28/
tion
20/12/4
EDOCRn 
(n = 0, 1) _


Bit 27/
19/11/3



FEC
Bit 26/
18/10/2



AEC
Bit 25/
17/9/1




Bit 24/
16/8/0




Rev. 2.00 Dec. 07, 2005 Page 943 of 950
REJ09B0079-0200