SH7710 Datasheet, PDF (966/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Appendix
Pin Name
Reset
Power-Down States _{Release of}
Power-on Manual Software
Bus
Handling of
I/O
Reset
Reset Standby Sleep
Mastership Unused Pins
Vss-PLL1





Vss*⁷
Vcc-PLL2





Vcc*⁷
Vss-PLL2





Vss*⁷
[Legend]
I:
Input state
i:
Input state (however, input is fixed by the internal logic)
O: Output state (undefined although the level is high or low)
L:
Low-level output
H: High-level output
Z:
High impedance (input or output buffer off)
V:
Input/output buffer off, pull-up on
M: Input buffer on, output buffer off, pull-up on
K:
Output buffer on or input buffer off (pull-up on or off), depending on register settings
P:
Input or output depending on register settings
Notes:
1. Depends on clock mode.
2. The state is P when the port function is used.
3. The state is K when the port function is used.
4. The state is Z or H depending on register settings.
5. The state is Z or O depending on register settings.
6. The state is Z when the Ethernet controller function is used.
7. To avoid the power friction, Vcc-PLL1, Vcc-PLL2, Vss-PLL1, Vss-PLL2, and other Vcc
and Vss should be wired in three independent patterns from the board power-supply
source.
Rev. 2.00 Dec. 07, 2005 Page 924 of 950
REJ09B0079-0200