SH7710 Datasheet, PDF (660/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Figure 17.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
(a) 16-bit stereo data
31
24 23
16 15
87
0
Lch.data
Rch.data
(b) 16-bit monaural data
31
24 23
16 15
87
0
Data
(c) 8-bit monaural data
31
24 23
16 15
87
0
Data
(d) 16-bit stereo data (left and right same audio output) data
31
24 23
16 15
87
0
Data
Figure 17.5 Transmit/Receive Data Bit Alignment
Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in
unshaded areas is not transmitted or received.
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for the transmit data, specify
the TLREP bit in SITDAR. Tables 17.5 and 17.6 show the audio mode specification for transmit
data and that for receive data, respectively. To execute 8-bit monaural transmission or reception,
use the left channel.
Rev. 2.00 Dec. 07, 2005 Page 618 of 950
REJ09B0079-0200