SH7710 Datasheet, PDF (497/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus mastership
is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the
SDRAM refresh.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
Rev. 2.00 Dec. 07, 2005 Page 455 of 950
REJ09B0079-0200