SH7710 Datasheet, PDF (540/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
Bit Bit Name Initial Value R/W Description
0 STR0
0
R/W Counter Start 0
Selects whether to run or halt TCNT0.
0: TCNT0 count halted
1: TCNT0 counts
14.2.2 Timer Control Registers (TCR)
The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has
three TCR registers, one for each channel.
The TCR registers control the issuance of interrupts when the flag indicating timer counters
(TCNT) underflow has been set to 1, and also carry out counter clock selection.
The TCR registers are 16-bit readable/writable registers. They are initialized to H'0000 by a
power-on reset and manual reset, but are not initialized, and retain their contents, in standby mode.
Bit Bit Name
15 or 9 
8
UNF
7, 6 
Initial Value R/W
All 0
R
0
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Underflow Flag
Status flag that indicates occurrence of a TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
0 is written to UNF
1: TCNT has underflowed
[Setting condition]
TCNT underflows*
Note: * Contents do not change when 1 is written to
UNF.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Dec. 07, 2005 Page 498 of 950
REJ09B0079-0200