SH7710 Datasheet, PDF (258/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is
valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write-
back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address
holds the physical address used in the external memory access. It is composed of 22 bits (address
bits 31–10) used for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 12, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on or manual reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address can be registered in the cache. When an entry is registered, LRU shows which of the four
ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used
(LRU) algorithm is used to select the way.
Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 6.1 shows the
relationship between the LRU bits and the way to be replaced when the cache locking mechanism
is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section
6.2.2, Cache Control Register 2 (CCR2).) If a bit pattern other than those listed in table 6.1 is set
in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits
by software, set one of the patterns listed in table 6.1.
The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual
reset.
Table 6.1 LRU and Way Replacement (when Cache Locking Mechanism is Disabled)
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
2
1
0
Rev. 2.00 Dec. 07, 2005 Page 216 of 950
REJ09B0079-0200