SH7710 Datasheet, PDF (218/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
SPC Saved by Exception in Repeat Control Period: If an exception is accepted in the repeat
control period while the repeat counter (RC[11:0]) in the SR register is two or greater, the program
counter to be saved may not indicate the value to be returned correctly. To execute the repeat
control after returning from an exception processing, the return address must indicate an
instruction prior to a repeat detection instruction. Accordingly, if an exception is accepted in
repeat control period, an exception other than re-execution type exception by a repeat detection
instruction cannot return to the repeat control correctly.
Table 4.3 SPC Value when Re-Execution Type Exception Occurs in Repeat Control
(RC[11:0] ≥ 2)
Instruction where
Exception Occurs 1
Number of Instructions in Repeat Loop
2
3
4 or Greater
RptDtct
RptDtct
RptDtct
RptDtct
RptDtct
RptDtct1
RptDtct1
RptDtct1
RptDtct1
RptDtct1
RptDtct2

RptDtct1
RptDtct1
RS-4
RptDtct3


RptDtct1
RS-2
Note:
The following labels are used here.
RptDtct: Repeat detection instruction address
RptDtct1: An instruction address one instruction following the repeat detection instruction
RptDtct2: An instruction address two instruction following the repeat detection instruction
RptDtct3: An instruction address three instruction following the repeat detection instruction
RS:
Repeat start instruction address
If a re-execution type exception is accepted at an instruction in the hatched areas above, a
return address to be saved in the SPC is incorrect. If RC[11:0] is 1 or 0, a correct return
address is saved in the SPC.
Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is
executed at the address following RptDtct1, a general illegal instruction exception occurs. For
details on an address to be saved in the SPC, refer to the description in section 4.4.3, SPC Saved
by Exception in Repeat Control Period.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE
LDC Rn, SR, LDC @Rn+, SR, LDC Rn, RE, LDC @Rn+, RE, LDC Rn,RS, LDC @Rn+, Rs
Rev. 2.00 Dec. 07, 2005 Page 176 of 950
REJ09B0079-0200