SH7710 Datasheet, PDF (980/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Page Revision (See Manual for Details)
Section 15 Realtime Clock (RTC) 507
15.2 Input/Output Pins
Table 15.1 Pin Configuration
Note: 1. Pull up (VccQ-RTC) the EXTAL2 pin, and
open (NC) the XTAL2 pin when the realtime
clock (RTC) is not used.
2. RTC in this LSI does not operate even if
VccQ-RTC is turned on. The crystal
oscillator circuit for RTC operates with VccQ-
RTC. The control circuit and the RTC
counter operate with Vcc (common to the
internal circuit). Therefore, all power supplies
other than VccQ-RTC should always be
turned on even if only RTC operates.
15.5.4 Usage Note about RTC
Power Supply
530 Added
Section 17 Serial I/O with FIFO 614
Sampling Rate
(SIOF)
Frame Length 8 kHz
96 kHz
17.4 Operation
17.4.1 Serial Clocks
32 bits
256 kHz
3.072 MHz
Table 17.2 SIOF Serial Clock
Frequency
Figure 17.13 Transmission and 631
Reception Timings (8-Bit
Monaural Data (1))
Figure 17.15 Transmission and 632
Reception Timings (16-Bit
Monaural Data (1))
Figure 17.17 Transmission and 633
Reception Timings (16-Bit Stereo
Data (2))
Figure 17.18 Transmission and 633
Reception Timings (16-Bit Stereo
Data (3))
Setting: TRMD = 00or10, REDG = 0,
FL = 0000 (frame legth: 8 bits)
TDLE = 1,
TDLA3 to TDLA0 = 0000, TDRE = 0, TDRA3 to TDRA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000, RDRE = 0, RDRA3 to RDRA0 = 0000,
CD0E = 0,
CD0A3 to CD0A0 = 0000, CD1E = 0, CD1A3 to CD1A0 = 0000
Setting: TRMD = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 0,
REDG = 0,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length: 64 bits)
TDRE = 0, TDRA3 to TDRA0 = 0000,
RDRE = 0, RDRA3 to RDRA0 = 0000,
CD1E = 0, CD1A3 to CD1A0 = 0000
Setting: TRMD = 01, REDG = 1,
TDLE = 1, TDLA3 to TDLA0 = 0000,
RDLE = 1, RDLA3 to RDLA0 = 0001,
CD0E = 0, CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length: 64 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0011,
CD1E = 0, CD1A3 to CD1A0 = 0000
Setting: TRMD = 00 or 10, REDG = 0,
FL = 1110 (frame length: 128 bits),
TDLE = 1,
TDLA3 to TDLA0 = 0000, TDRE = 1, TDRA3 to TDRA0 = 0010,
RDLE = 1,
RDLA3 to RDLA0 = 0000, RDRE = 1, RDRA3 to RDRA0 = 0010,
CD0E = 1,
CD0A3 to CD0A0 = 0001, CD1E = 1, CD1A3 to CD1A0 = 0011
Section 18 Ethernet Controller
(EtherC)
18.3.2 EtherC Mode Register
(ECMR)
645 Bit
13
Bit Name
R/W
MCT
R/W
Rev. 2.00 Dec. 07, 2005 Page 938 of 950
REJ09B0079-0200