SH7710 Datasheet, PDF (716/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value
20
RINT50 0
19
RINT40 0
18
RINT30 0
17
RINT20 0
16
RINT10 0
15 to 12 
All 0
11
TINT41 0
10
TINT31 0
9
TINT21 0
8
TINT11 0
7
OVF1
0
R/W Description
R/W MAC-0 Residual Bit Frame Receive
Set to 1 when frames containing residual bits (less than
an 8-bit unit) are received in the MAC-0
R/W MAC-0 Exceeding Byte Frame Receive
Set to 1 when frames exceeding the value set by
RFLR0 are received in the MAC-0
R/W MAC-0 Less 64-Byte Frame Receive
Set to 1 when frames with a length of less than 64
bytes are received in the MAC-0
R/W MAC-0 Frame Receive Error
Set to 1 when a receive error is detected on the RX-ER
pin input from the PHY in the MAC-0
R/W MAC-0 CRC Error Frame Receive
Set to 1 when a receive frame results in a CRC error in
the MAC-0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W MAC-1 Carrier Not Detect
Set to 1 when a carrier not detect has occured in the
MAC-1
R/W MAC-1 Carrier Lost
Set to 1 when a carrier is lost during data transmission
in the MAC-1
R/W MAC-1 Collision Detect
Set to 1 when a collision of frames is detected in the
MAC-1
R/W MAC-1 Transmission Time Out
Set to 1 when frames were unable to be transmitted in
16 transmission attempts including the retransfer in the
MAC-1
R/W Port 1 to 0 TSU FIFO Overflow Detect
Set to 1 when a port 1 to 0 TSU FIFO overflow has
occured
Rev. 2.00 Dec. 07, 2005 Page 674 of 950
REJ09B0079-0200