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| SH7710 Datasheet, PDF (458/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Tw
Td1
Td2
Td3
Td4
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.15 Burst Read Wait Specification Timing (Auto Precharge)
Rev. 2.00 Dec. 07, 2005 Page 416 of 950
REJ09B0079-0200
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