SH7710 Datasheet, PDF (300/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name
5
TXI0R
4
ERI0R
3 to 0 
Initial Value R/W
0
R
0
R
All 0
R
Description
TXI0 Interrupt Request
Indicates whether the TXI0 (SIOF0) interrupt
request is generated.
0: TXI0 interrupt request is not generated
1: TXI0 interrupt request is generated
ERI0 Interrupt Request
Indicates whether the ERI0 (SIOF0) interrupt
request is generated.
0: ERI0 interrupt request is not generated
1: ERI0 interrupt request is generated
Reserved
These bits are always read as 0. The write value
should always be 0.
8.4.11 Interrupt Request Register 8 (IRR8)
IRR8 is an 8-bit register that indicates whether interrupt requests from the SIOF1 are generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
Bit Name Initial Value R/W Description
7
CCI1R
0
R
CCI1 Interrupt Request
Indicates whether the CCI1 (SIOF1) interrupt
request is generated.
0: CCI1 interrupt request is not generated
1: CCI1 interrupt request is generated
6
RXI1R
0
R
RXI1 Interrupt Request
Indicates whether the RXI1 (SIOF1) interrupt
request is generated.
0: RXI1 interrupt request is not generated
1: RXI1 interrupt request is generated
Rev. 2.00 Dec. 07, 2005 Page 258 of 950
REJ09B0079-0200