SH7710 Datasheet, PDF (276/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 X/Y Memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC, E-DMAC and
IPSEC). In a program that requires high performance, it is advisable to access the X/Y memory
from space P2 or Uxy.
The relationship described above is summarized in table 7.2.
Table 7.2 MMU and Cache Settings
Setting
Logical Address Space and Access Enabled or Disabled
CCR1.CE
MMUCR.AT P0, U0
P1
P2, Uxy
P3
0
0
B
B
A
B
0
1
B
B
A
B
1
0
X
X
A
X
1
1
C
X
A
C
[Legend] A:
B:
C:
X:
Accessible (recommended)
Accessible
Accessible (Note that MMU page attribute must be specified as cache disabled
by clearing the C bit to 0.)
Not Accessible
7.3.4 Sleep Mode
In sleep mode, I bus master modules such as the DMAC, E-DMAC and IPSEC cannot access the
X/Y memory.
7.3.5 Address Error
If writing that may causes an address error is performed on the X/Y memory, the contents of the
X/Y memory are not guaranteed.
Rev. 2.00 Dec. 07, 2005 Page 234 of 950
REJ09B0079-0200