SH7710 Datasheet, PDF (616/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.12 shows a sample the SCIF initialization flowchart.
Start Initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits in SCFCR
to 1 and clear buffer of FIFO
Read BRK, DR, and ER flags in SCFSR
and clear the flags by writing 0
Set CKE1 and CKE0 bits in SCSCR
(TE, RE, TIE, and RIE bits are
cleared to 0)
Set transmit or receive format in SCSMR
Set value in SCBRR
Wait
1. Keep the TE and RE bits cleared to 0 until initialization
has been completed.
2. Set the CKE1 and CKE0 bits.
3. Set the transfer or receive format in SCSMR.
4. Write a value corresponding to the bit rate in SCBRR.
(Not necessary if an external clock is used.) After this
setting wait for at least 1-bit interval.
5. Set the external pins. Specifies the pins as RxD input
in reception and TxD output in transmission. Set the
SCIFnCK input/output according to the CKE1 and
CKE0 settings.
6. Set the TE bit or RE bit in SCSCR to 1. Also, set the
TIE, RIE, and REIE bits. At this time, the TxD, RxD,
and SCIFnCK pins can be used. In transmission, the
TxD pin is in the mark state. When reception in
clock synchronous mode and synchronous clock output
(clock master) are selected, a clock is output from the
SCIFnCK pin.
No
1-bit interval elapsed?
Yes
Set RTRG1, RTRG0, TTRG1, and
TTRG0 bits in SCFCR. Clear TFRST
and RFRST bits to 0.
Set external pins (SCIFnCK, TxD, RxD)
Set TE and RE bits in SCSCR to 1
and set RIE, TIE, and REIE bits
End
Figure 16.12 Sample the SCIF Initialization Flowchart
Rev. 2.00 Dec. 07, 2005 Page 574 of 950
REJ09B0079-0200