SH7710 Datasheet, PDF (983/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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19.2.8 Transmit/Receive Status 743
Copy Enable Register (TRSCER)
TRSCER indicates whether multicast address frame
receive status information reported by bit 7 in EESR is
reflected in the RFE bit in the corresponding register
(for details of descriptor descriptions, see section
19.3.1, Descriptors and Descriptor List).
The RMAFCE bit in this register corresponds to bit 7 in
EER. When the RMAFCE bit is cleared to 0, the
receive status (bit 7 in ESSR) is reflected in the REF bit
in the receive descriptor. When this bit is set to 0, the
status is not reflected in the descriptor even if the
corresponding source occurs. The RMAFCE bit is
cleared to 0 after a power-on reset and manual reset.
Initial
Bit Bit Name Value R/W Description
31 to 
8
All 0 R
Reserved
These bits are always read as 0.
The write value should always be
0.
7
RMAFCE 0
R/W RMAF Bit Copy Directive
0: Reflects the RMAF bit status in
the RFE bit of the receive
descriptor
1: Occurrence of the corresponding
source is not reflected in the
RFE bit of the receive
descriptor
6 to 0 
All 0 R Reserved
These bits are always read as 0.
The write value should always be
0.
19.2.19 Receive Data Padding
Insert Register (RPADIR)
753 Deleted
Rev. 2.00 Dec. 07, 2005 Page 941 of 950
REJ09B0079-0200