SH7710 Datasheet, PDF (494/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5.9 Burst ROM (Clock Synchronous) Interface
The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous
burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as
a normal space. This interface is valid only for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be
inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the
number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR.
While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first
access cycle and an external wait input is also valid for the first access cycle.
If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the
burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width
for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For
example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid
16-bit data is read six times.
These invalid data read cycles increase the memory access time and degrade the program
execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or
16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the
same way as normal space access.
Note: The burst ROM (clock synchronous) must be accessed as cacheable space.
T1
Tw
Tw
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2
CKIO
Address
CSn
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 12.45 Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Wait Cycles inserted in Second and Subsequent Accesses = 1)
Rev. 2.00 Dec. 07, 2005 Page 452 of 950
REJ09B0079-0200