SH7710 Datasheet, PDF (662/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Table 17.7 Setting for Number of Control Data Channels
Number of Channels
1
2
CD0E
1
1
Bit
CD1E
0
1
17.4.5 Control Data Interface
Control data performs control command output to the CODEC and status input from the CODEC.
The SIOF supports the following two control data interface methods.
• Control by slot position
• Control by secondary FS
Control data is valid only when slot length is specified as 16 bits and MSB-first
transmission/reception is selected.
Control by Slot Position (Master Mode 1): Control data is transferred for all frames transmitted
or received by the SIOF by specifying the slot position of control data. This method can be used in
both SIOF master and slave modes. Figure 17.7 shows an example of control data interface timing
by slot position control.
Note: When using this control method, use PCLK as the master clock (master clock selection
(MSSEL) = 1).
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Slot No.0
Control
channel 0
Rch.DATA
Control
channel 0
Slot No.1 Slot No.2 Slot No.3
Setting: TRMD = 00 or 10, REDG = 0,
TDLE = 1,
TDLA3 to TDLA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000,
CD0E = 1,
CD0A3 to CD0A0 = 0001,
FL = 1110 (Frame length: 128 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0010,
CD1E = 1, CD1A3 to CD1A0 = 0011
Figure 17.7 Control Data Interface (Slot Position)
Rev. 2.00 Dec. 07, 2005 Page 620 of 950
REJ09B0079-0200