SH7710 Datasheet, PDF (233/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
5.2.2 Page Table Entry Register Low (PTEL)
The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
Initial
Bit
Bit Name Value R/W Description
31 to 29 
All 0
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 10 PPN

R
Number of Physical Page
9

0
R/W Page management information
8
V

For more details, see section 5.3, TLB Functions
7

0
6, 5
PR

4
SZ

3
C

2
D

1
SH

0

0
5.2.3 Translation Table Base Register (TTB)
The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
5.2.4 MMU Control Register (MMUCR)
The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU
settings described in figure 5.3. Any program that modifies MMUCR should reside in the P1 or P2
area.
Rev. 2.00 Dec. 07, 2005 Page 191 of 950
REJ09B0079-0200