SH7710 Datasheet, PDF (526/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
RD
WEn
DACKn
(Active-Low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 13.6 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary
memory, Destination: Ordinary memory)
2. Single Address Mode
In single address mode, either the transfer source or transfer destination external device is
accessed (selected) by means of the DACK signal, and the other device is accessed by address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in
the case of transfer between external memory and an external device with DACK shown in
figure 13.7, when the external device outputs data to the data bus, that data is written to the
external memory in the same bus cycle.
Rev. 2.00 Dec. 07, 2005 Page 484 of 950
REJ09B0079-0200