SH7710 Datasheet, PDF (439/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5.4 CSn Assert Period Expansion
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 12.11 shows an example. A Th cycle and a Tf cycle are
added before and after an ordinary cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
Th
T1
T2
Tf
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn(BEn)
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.11 CSn Assert Period Expansion
Rev. 2.00 Dec. 07, 2005 Page 397 of 950
REJ09B0079-0200