SH7710 Datasheet, PDF (804/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a) Receive Descriptor 0 (RD0)
The user sets the descriptor valid/invalid bit and sets whether the descriptor represents the end of
the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the start of a read by the E-
DMAC. After completion of receive DMA transfer of an Ethernet frame by the E-DMAC, the E-
DMAC disables the descriptor valid/invalid bit and writes status information. This operation is
referred to as write-back.
When using RD0, the user should write desired values to bits 31 and 30 according to the
descriptor configuration. Write 0 to bits 29 to 0.
Initial
Bit
Bit Name Value R/W Description
31
RACT
0
R/W Receive Descriptor Valid/Invalid
Indicates whether the corresponding descriptor is
valid or invalid. To make this bit valid, prepare a
receive buffer (user-specified receive data storage
destination) beforehand, then write 1 to this bit. The
E-DMAC clears this bit to 0 upon completion of data
transfer.
0: Indicates that the receive descriptor is invalid
Indicates the initial setting state, the state after 0 is
written, or (in case the user writes 1 to this bit) that
this bit is cleared to 0 because of completion of the
processing of the E-DMAC data transfer.
If this state is recognized when the E-DMAC reads
a descriptor, the E-DMAC clears the RR bit in
EDRRR to 0, and halts transfer operation related
to reception by the E-DMAC.
1: Indicates that the receive descriptor is valid
Indicates that data is not transferred yet after the
user writes 1 to this bit, or that data is being
transferred.
When there is a descriptor row (descriptor list)
consisting of multiple continuous descriptors, the
E-DMAC can continue operation when this bit of
the next descriptor is valid.
Rev. 2.00 Dec. 07, 2005 Page 762 of 950
REJ09B0079-0200