SH7710 Datasheet, PDF (533/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High active)
CPU
Burst acceptance
CPU
DMAC
Non sensitive period
DMAC
Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
DMAC
3rd
acceptance
Acceptance
start
Acceptance
start
Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
Bus cycle
DREQ
DACK
(High active)
TEND
(High active)
DMAC
CPU
End of DMA transfer
DMAC
CPU
CPU
Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection)
Rev. 2.00 Dec. 07, 2005 Page 491 of 950
REJ09B0079-0200