SH7710 Datasheet, PDF (921/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Tr
Tc1
Trwl
t_AD1
t_AD1
t_AD1
Row address
Column
address
t_AD1
t_AD1
t_AD1
Write A
command
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_BSD
CKE
t_DACD
(High)
t_DACD
DACKn*²
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 25.26 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 2 Cycle)
Rev. 2.00 Dec. 07, 2005 Page 879 of 950
REJ09B0079-0200