SH7710 Datasheet, PDF (287/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Interrupt Source
Interrupt Code
Interrupt
Priority
Priority
IPR
within IPR Default
(Initial Value) (Bit Numbers) Setting Unit Priority
RTC ATI
H′480*²
0 to 15 (0) IPRA (3 to 0) High
High
PRI
H′4A0*²
CUI
H′4C0*²
Low
WDT ITI
H′560*²
0 to 15 (0) IPRB (15 to 12) 
REF RCMI
H′580*²
0 to 15 (0) IPRB (11 to 8) 
Low
Notes: 1. INTEVT2 code
2. The code set in INTEVT is as same as INTEVT2.
3. The code that indicates the interrupt level (H′200 to H′3C0) is set in INTEVT. For details
on correspondence between the interrupt level and INTEVT, see table 8.4.
Table 8.4 Interrupt Level and INTEVT Code
Interrupt Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
INTEVT Code
H′200
H′220
H′240
H′260
H′280
H′2A0
H′2C0
H′2E0
H′300
H′320
H′340
H′360
H′380
H′3A0
H′3C0
Rev. 2.00 Dec. 07, 2005 Page 245 of 950
REJ09B0079-0200