SH7710 Datasheet, PDF (641/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
8
RXE
0
R/W Reception Enable
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal). When
the 1 setting for this bit becomes valid, the SIOF begins
the reception of data from the RXD_SIO pin. When
receive data is stored in receive FIFO, the SIOF issues a
reception transfer request according to the setting of the
RFWM bit in SIFCTR. This bit is initialized by a receive
reset.
0: Disables data reception from RXD_SIO
1: Enables data reception from RXD_SIO
7 to 2 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
TXRST 0
R/W Transmission Reset
This bit setting becomes valid immediately. When the 1
setting for this bit becomes valid, the SIOF immediately
sets transmit data from the TXD_SIO pin to 1, and
initializes the transmission data register and transmission-
related status register. The following are initialized.
• SITDR
• Transmit FIFO write/read pointer
• TCRDY, TFEMP, and TDREQ bits in SISTR
• TXE bit
As the SIOF is cleared automatically at the completion of
reset operation, this bit is always read as 0.
0: Transmission operation is not reset
1: Resets transmission operation
Rev. 2.00 Dec. 07, 2005 Page 599 of 950
REJ09B0079-0200