SH7710 Datasheet, PDF (200/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
4.1.4 Interrupt Event Register 2 (INTEVT2)
INTEVT2 is assigned to address H′A4000000 and consists of the exception code. Exception codes
to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
Bit
Bit Name
31 to 12 
11 to 0 INTEVT2
Initial Value R/W
All 0
R

R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
4.1.5 Exception Address Register (TEA)
TEA is assigned to address H′FFFFFFFC and the logical address for an exception occurrence is
stored in this register when an exception related to memory accesses occurs. TEA can be modified
using the software.
Bit
Bit Name
31 to 0 TEA
Initial Value R/W
0
R/W
Description
Logical address for Exception Occurrence
Rev. 2.00 Dec. 07, 2005 Page 158 of 950
REJ09B0079-0200