SH7710 Datasheet, PDF (254/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
Both reading and writing use the longword of the data array specified by the entry address and
way number. The access size of the data array is fixed at longword.
(1) TLB Address Array Access
• Read Access
31
24 23
17 16
12 1110 9 8 7 6
2 10
Address Field 1 1 1 1 0 0 1 0 * ^{. . . . . . . . . . . .} *
VPN
* * W 0 * ^{. . . . . . . . .} * 00
31
Data Field
VPN
17 16
12 1110 9 8 7
0
0 ^{. . . . . . .} 0 VPN 0 V
ASID
• Write Access
31
24 23
17 16
12 1110 9 8 7 6
2 10
Address Field 1 1 1 1 0 0 1 0 * ^{. . . . . . . . . . . .} *
VPN
* * W 0 * ^{. . . . . . . . .} * 00
31
Data Field
VPN
17 16
12 1110 9 8 7
0
* ^{. . . . . . .} * VPN * V
ASID
VPN: Virtual Page Number
V: Valid Bit
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
ASID: Address Space Identifier
*: Don’t Care Bit
(2) TLB Data Array Access
• Read/Write Access
31
24 23
17 16
12 1110 9 8 7
2 10
Address Field 1 1 1 1 0 0 1 1 * ^{. . . . . . . . . . . .} *
VPN
* * W * ^{. . . . . . . . . . .} * 00
Data Field
31 29 28
000
PPN
10 9 8 7 6 5 4 3 2 1 0
X V X PR SZ C D SH X
PPN: Physical Page Number
PR: Protection Key Field
C: Cacheable Bit
SH: Share Status Bit
VPN: Virtual Page Number
X: 0 for Read, Don’t Care Bit for Write
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
V: Valid Bit
SZ: Page-Size Bit
D: Dirty bit
*: Don’t Care Bit
Figure 5.14 Specifying Address and Data for Memory-Mapped TLB Access
Rev. 2.00 Dec. 07, 2005 Page 212 of 950
REJ09B0079-0200