SH7710 Datasheet, PDF (315/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
Initial
Bit
Bit Name Value R/W Description
5
IDB1
0
R/W Instruction Fetch/Data Access Select B
4
IDB0
0
R/W Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
data access cycle
3
RWB1 0
R/W Read/Write Select B
2
RWB0 0
R/W Select the read cycle or write cycle as the bus cycle of
the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
1
SZB1
0
R/W Operand Size Select B
0
SZB0
0
R/W Select the operand size of the bus cycle for the channel
B break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Rev. 2.00 Dec. 07, 2005 Page 273 of 950
REJ09B0079-0200