SH7710 Datasheet, PDF (673/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Slot No.0
1-bit delay
Setting: TRMD = 00or10, REDG = 0,
TDLE = 1,
TDLA3 to TDLA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000,
CD0E = 0,
CD0A3 to CD0A0 = 0000,
FL = 0000 (frame legth: 8 bits)
TDRE = 0, TDRA3 to TDRA0 = 0000,
RDRE = 0, RDRA3 to RDRA0 = 0000,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 17.13 Transmission and Reception Timings (8-Bit Monaural Data (1))
8-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, frame length = 16 bits
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch.DATA
Slot No.0
Slot No.1
1-bit delay
Setting: TRMD = 00or10, REDG = 0,
TDLE = 1,
TDLA3 to TDLA0 = 0000,
RDLE = 1,
RDLA3 to RDLA0 = 0000,
CD0E = 0,
CD0A3 to CD0A0 = 0000,
FL = 0100 (frame length: 16 bits)
TDRE = 0, TDRA3 to TDRA0 = 0000,
RDRE = 0, RDRA3 to RDRA0 = 0000,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 17.14 Transmission and Reception Timings (8-Bit Monaural Data (2))
16-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for
transmit and receive data, frame length = 64 bits
Rev. 2.00 Dec. 07, 2005 Page 631 of 950
REJ09B0079-0200