SH7710 Datasheet, PDF(740/996 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7710 Datasheet, PDF (740/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 18 Ethernet Controller (EtherC)

18.3.44 CAM Entry Table 0 to 31 H Registers (TSU_ADRH0 to TSU_ADRH31)

TSU_ADRH0 to TSU_ADRH31 are entry tables referred by the CAM in reception and relay. This

register sets the upper 32 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses

can be registered. To refer to input signals on the CAMSEN0 and CAMSEN 1 pins, do not set the

same MAC address set by this register to the entry tables of the external CAM.

Initial

Bit

Bit Name Value

R/W Description

31 to 0 ADRHn31 to All 0

ADRHn0

(n: 0 to 31)

R/W MAC Address Bit

These bits set the upper 32 bits of the MAC address.

When the MAC address is 01-23-45-67-89-AB

(displayed in hexadecimal), Hâ²01234567 is set to this

register.

Notes: Set the CAM entry table as follows:

1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0.

2. Set the upper 32 bits of the MAC address by TSU_ADRH0 to TSU_ADRH31.

3. Set the lower 16 bits of the MAC address by TSU_ADRL0 to TSU_ADRL31.

Rev. 2.00 Dec. 07, 2005 Page 698 of 950

REJ09B0079-0200

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