SH7710 Datasheet, PDF (193/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.6.5 Operation Code Map in DSP Mode
Table 3.40 shows the operation code map including an instruction codes extended in the DSP
mode.
Table 3.40 Operation Code Map
Instruction Code Fx: 0000
MSB
LSB MD: 00
0000 Rn Fx 0000
0000 Rn Fx 0001
0000 Rn 00MD 0010 STC SR, Rn
0000 Rn 01MD 0010 STC SPC, Rn
0000 Rn 10MD 0010 STC R0_BANK, Rn
0000 Rn 11MD 0010 STC R4_BANK, Rn
0000 Rm 00MD 0011 BSRF Rm
0000 Rm 10MD 0011 PREF @Rm
0000 Rn
Rm 01MD MOV.B Rm, @(R0,
Rn)
0000 0000 00MD 1000 CLRT
0000 0000 01MD 1000 CLRS
0000 0000 10MD 1000
0000 0000 11MD 1000
0000 0000 Fx 1001 NOP
0000 0000 Fx 1010
0000 0000 Fx 1011 RTS
0000 Rn Fx 1000
0000 Rn Fx 1001
0000 Rn 00MD 1010 STS MACH, Rn
0000 Rn 01MD 1010
0000 Rn 10MD 1010 STS X0, Rn
0000 Rn Fx 1011
Fx: 0001
MD: 01
STC GBR, Rn
STC MOD, Rn
STC R1_BANK, Rn
STC R5_BANK, Rn
MOV.W Rm,
@(R0, Rn)
SETT
SETS
DIV0U
SLEEP
STS MACL, Rn
STS X1, Rn
Fx: 0010
MD: 10
STC VBR, Rn
STC RS, Rn
STC R2_BANK, Rn
STC R6_BANK, Rn
BRAF Rm
MOV.L Rm,
@(R0, Rn)
CLRMAC
RTE
MOVT Rn
STS PR, Rn
STS DSR, Rn
STS Y0, Rn
Fx: 0011 to 1111
MD: 11
STC SSR, Rn
STC RE, Rn
STC R3_BANK, Rn
STC R7_BANK, Rn
MUL.L Rm, Rn
LDTLB
STS A0, Rn
STS Y1, Rn
Rev. 2.00 Dec. 07, 2005 Page 151 of 950
REJ09B0079-0200