SH7710 Datasheet, PDF (542/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
When a TCNT count-down results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in TCR of the relevant channel is set. The TCOR value is simultaneously set in TCNT
itself and the count-down continues from that value.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and
retains its contents, in standby mode.
14.3 TMU Operation
Each of the three channels has a 32-bit TCNT and a 32-bit TCOR. TCNT counts down. The auto-
reload function enables synchronized counting and counting by external events.
14.3.1 Counter Operation
When the STR0 to STR2 bits in TSTR are set to 1, the corresponding TCNT starts counting.
When TCNT underflows, the underflow flag (UNF) of the corresponding TCR is set. At this time,
if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is
copied from TCOR to TCNT and the down-count operation is continued.
Count Operation Setting Procedure: An example of the procedure for setting the count
operation is shown in figure 14.2.
Rev. 2.00 Dec. 07, 2005 Page 500 of 950
REJ09B0079-0200