SH7710 Datasheet, PDF (119/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Before entering the exception handling state, all bits including the DSP extension bits of the SR
registers are saved in the SSR. Before returning from the exception handling, all bits including the
DSP extension bits of the SR must be restored. If the repeat control must be recovered before
entering the exception handling state, the RS and RE registers must be recovered to the value that
existed before exception handling. In addition, if it is necessary to recover modulo control before
entering the exception handling state, the MOD register must be recovered to the value that
existed before exception handling.
3.2.4 DSP Registers
The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status
register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers
with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G
and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation
result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit
of the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions.
39 32 31
A0G
A0
A1G
A1
M0
M1
X0
X1
Y0
Y1
0
Initial value
DSR : All 0
Others: Undefined
(a) DSP data registers
31
12 11
98 7 6 5 43
10
....................................................
TS[2:0] TC GT Z N V CS[2:0] DC
(b) DSP status register (DSR)
Figure 3.3 DSP Register Configuration
Rev. 2.00 Dec. 07, 2005 Page 77 of 950
REJ09B0079-0200