SH7710 Datasheet, PDF (618/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-
data-empty interrupt (TXI) request is generated. If and external clock is specified, the SCIF
outputs data in synchronization with the input clock. Serial transmit data is output in order
from LSB to MSB from the TxD pin.
3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then
the state of the TxD pin is held.
4. After serial transmission has completed, the SCIFnCK pin is fixed to high.
Figure 16.14 shows an example of the SCIF transmit operation.
Serial
clock
Serial
data
LSB
Bit 0
Bit 1
MSB
Bit 7 Bit 0
Bit 1
Bit 6
Bit 7
TDFE
TEND
TXI
request
TXI handling routine writes
data in SCFTDR and clears
the TDFE flag to 0
TXI
request
1 frame
Figure 16.14 Example of the SCIF Transmit Operation
Rev. 2.00 Dec. 07, 2005 Page 576 of 950
REJ09B0079-0200