SH7710 Datasheet, PDF (771/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
• Receive missed-frame counter register (RMFCR0)
• Transmit FIFO threshold register (TFTR0)
• FIFO depth register (FDR0)
• Receiving method control register (RMCR0)
• E-DMAC operation control register (EDOCR0)
• Receive buffer write address register (RBWAR0)
• Receive descriptor fetch address register (RDFAR0)
• Transmit buffer read address register (TBRAR0)
• Transmit descriptor fetch address register (TDFAR0)
• Overflow alert FIFO threshold register (FCFTR0)
• Transmit interrupt register (TRIMD0)
Channel 1:
• E-DMAC mode register (EDMR1)
• E-DMAC transmit request register (EDTRR1)
• E-DMAC receive request register (EDRRR1)
• Transmit descriptor list address register (TDLAR1)
• Receive descriptor list address register (RDLAR1)
• EtherC/E-DMAC status register (EESR1)
• EtherC/E-DMAC status interrupt permission register (EESIPR1)
• Transmit/receive status copy enable register (TRSCER1)
• Receive missed-frame counter register (RMFCR1)
• Transmit FIFO threshold register (TFTR1)
• FIFO depth register (FDR1)
• Receiving method control register (RMCR1)
• E-DMAC operation control register (EDOCR1)
• Receive buffer write address register (RBWAR1)
• Receive descriptor fetch address register (RDFAR1)
• Transmit buffer read address register (TBRAR1)
• Transmit descriptor fetch address register (TDFAR1)
• Overflow alert FIFO threshold register (FCFTR1)
• Transmit interrupt register (TRIMD1)
Rev. 2.00 Dec. 07, 2005 Page 729 of 950
REJ09B0079-0200