SH7710 Datasheet, PDF (691/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Initial
Bit
Bit Name Value
0
ICD
0
Section 18 Ethernet Controller (EtherC)
R/W Description
R/W Illegal Carrier Detection
Indicates that the PHY-LSI has detected an illegal
carrier on the line. If a change in the signal input from
the PHY-LSI occurs before the software recognition
period, the correct information may not be obtained.
Refer to the timing specification for the PHY-LSI used.
0: PHY-LSI has not detected an illegal carrier on the
line
1: PHY-LSI has detected an illegal carrier on the line
18.3.4 EtherC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit Bit Name
31 to 3 
Initial
Value
All 0
2
LCHNGIP 0
1
MPDIP 0
0
ICDIP
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W LINK Signal Changed Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
R/W Magic Packet Detection Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
R/W Illegal Carrier Detection Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
Rev. 2.00 Dec. 07, 2005 Page 649 of 950
REJ09B0079-0200