SH7710 Datasheet, PDF (745/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.53 Transmit Frame Counter Register (Port 1) (Normal and Error Transmission)
(TXALCR1)
TXALCR1 is a 32-bit counter indicating the number of frames successfully transmitted and
frames transmitted with error in MAC-1. When the value in this register reaches H'FFFFFFFF, the
count is halted. The counter value is cleared to 0 by a read to this register. This register cannot be
written.
Initial
Bit
Bit Name Value
31 to 0 TC131 to All 0
TC100
R/W Description
R
Port 1 Transmit Frame Counter Bit
These bits indicate the number of frames successfully
transmitted and frames transmitted with error.
18.3.54 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1)
RXNLCR1 is a 32-bit counter indicating the number of frames successfully received in MAC-1.
When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is
cleared to 0 by a read to this register. This register cannot be written.
Initial
Bit
Bit Name Value
31 to 0 NRC131 to All 0
NRC100
R/W Description
R
Port 1 Receive Frame Counter Bit
These bits indicate the number of frames successfully
received.
Rev. 2.00 Dec. 07, 2005 Page 703 of 950
REJ09B0079-0200