SH7710 Datasheet, PDF (298/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
0
RCMIR
0
R
RCMI Interrupt Request
Indicates whether the RCMI (REF) interrupt
request is generated.
0: RCMI interrupt request is not generated
1: RCMI interrupt request is generated
8.4.9 Interrupt Request Register 5 (IRR5)
IRR5 is an 8-bit register that indicates whether interrupt requests from the IPSEC, DMAC, and E-
DMAC are generated. This register is initialized to H'00 by a power-on reset or manual reset, but
is not initialized in standby mode.
Bit
Bit Name Initial Value R/W Description
7
IPSECIR 0
R
IPSECI Interrupt Request
Indicates whether the IPSECI (IPSEC) interrupt
request is generated.
0: IPSECI interrupt request is not generated
1: IPSECI interrupt request is generated
6

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
5
DEI5R
0
R
DEI5 Interrupt Request
Indicates whether the DEI5 (DMAC) interrupt
request is generated.
0: DEI5 interrupt request is not generated
1: DEI5 interrupt request is generated
4
DEI4R
0
R
DEI4 Interrupt Request
Indicates whether the DEI4 (DMAC) interrupt
request is generated.
0: DEI4 interrupt request is not generated
1: DEI4 interrupt request is generated
3

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 2.00 Dec. 07, 2005 Page 256 of 950
REJ09B0079-0200