SH7710 Datasheet, PDF (431/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.5.2 Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of
the fact that mainly static RAM will be directly connected. When using SRAM with a byte-
selection pin, see section 12.5.7, Byte-Selection SRAM Interface. Figure 12.3 shows the basic
timings of normal space access. A no-wait normal access is completed in two cycles. The BS
signal is asserted for one cycle to indicate the start of a bus cycle.
CKIO
T1
T2
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
RD/WR
Write
WEn(BEn)
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
Rev. 2.00 Dec. 07, 2005 Page 389 of 950
REJ09B0079-0200