SH7710 Datasheet, PDF (770/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmit
descriptor 1
Receive
descriptor 1
Transmit
descriptor 0
Receive
descriptor 0
Transmit
buffer 1
Receive
buffer 1
Transmit
buffer 0
Receive
buffer 0
This LSI
Internal bus
External bus
interface
E-DMAC1
Internal
bus
interface
Descriptor
Information
Transmit
FIFO
Transmit DMAC
Descriptor
Information
Receive
FIFO
Receive DMAC
E-DMAC0
Internal
bus
interface
Descriptor
Information
Transmit DMAC
Descriptor
Information
Receive DMAC
Transmit
FIFO
Receive
FIFO
EtherC
External memory
Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers
19.2 Register Descriptions
The E-DMAC has the following registers. The number at the end of the register abbreviation
represents the number of corresponding E-DMAC (E-DMAC0 or E-DMAC1). In this section,
some numbers are not mentioned. For addresses and access sizes of these registers, see section 24,
List of Registers.
Channel 0:
• E-DMAC mode register (EDMR0)
• E-DMAC transmit request register (EDTRR0)
• E-DMAC receive request register (EDRRR0)
• Transmit descriptor list address register (TDLAR0)
• Receive descriptor list address register (RDLAR0)
• EtherC/E-DMAC status register (EESR0)
• EtherC/E-DMAC status interrupt permission register (EESIPR0)
• Transmit/receive status copy enable register (TRSCER0)
Rev. 2.00 Dec. 07, 2005 Page 728 of 950
REJ09B0079-0200