SH7710 Datasheet, PDF (91/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.4 CPU Instruction Formats
Instruction Format
0 type
15
0
xxxx xxxx xxxx xxxx
n type
15
0
xxxx nnnn xxxx xxxx
m type
15
0
xxxx mmmm xxxx xxxx
nm type
15
0
xxxx nnnn mmmm xxxx
Source
Operand
—
Destination
Operand
—
Sample Instruction
NOP
—
nnnn: register
MOVT Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register Control register or LDC Rm,SR
direct
system register
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register —
indirect
JMP @Rm
PC-relative using —
Rm
BRAF Rm
mmmm: register nnnn: register
direct
direct
ADD Rm,Rn
mmmm: register nnnn: register
indirect
indirect
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
MOV.L Rm,@Rn
MAC.W @Rm+,@Rn+
Rev. 2.00 Dec. 07, 2005 Page 49 of 950
REJ09B0079-0200