SH7710 Datasheet, PDF (125/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.5 Repeat Control Macros
Instruction
Operation
Number of
Execution
States
REPEAT RptStart, RptEnd, #imm Specifies RptStart as repeat start instruction, 3
RptEnd as repeat end instruction, and 8-bit
immediate data #imm as number of repetitions.
This macro is extended to three instructions:
LDRS, LDRE, and SETRC which are converted
correctly.
REPEAT RptStart, RptEnd, Rm
Specifies RptStart as repeat start instruction, 3
RptEnd as repeat end instruction, and the [11:0]
bits of Rm as number of repetitions. This macro
is extended to three instructions: LDRS, LDRE,
and SETRC which are converted correctly.
Using the repeat macros shown in table 3.5, examples 1 to 4 shown above can be simplified to
examples 5 to 8 as shown below.
• Example 5: Repeat loop consisting of 4 or more instructions (extended to the instruction
stream shown in example 1, above)
REPEAT RptStart, RptEnd, #4
Instr0
;
RptStart: instr1
; [Repeat start instruction]
... ...
;
... ...
;
instr(N-3)
;
instr(N-2)
;
instr(N-1)
RptEnd: instrN
;
;[Repeat end instruction]
• Example 6: Repeat loop consisting of three instructions (extended to the instruction stream
shown in example 2, above)
REPEAT RptStart, RptEnd, #4
instr0
;
RptStart: instr1
; [Repeat start instruction]
Instr2
;
RptEnd: instr3
; [Repeat end instruction]
Rev. 2.00 Dec. 07, 2005 Page 83 of 950
REJ09B0079-0200