SH7710 Datasheet, PDF (627/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ........................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Notes on DMAC Usage: To use an external clock source for a synchronous clock, the external
clock should be input after SCFTDR has been updated by the DMAC and then five cycles or more
of a peripheral operating clock has passed. If a transmit clock is input within four cycles after
SCFTDR has updated, erroneous operation may occur (figure 16.20).
SCIFnCK
t
TDFE
TxD
D0
D1
D2
D3
D4
D5
D6
D7
Note: To operate on an external clock, specify t as 4 cycles or more of a peripheral operating clock.
Figure 16.20 Sample Transfer of Synchronous Clock by DMAC
Rev. 2.00 Dec. 07, 2005 Page 585 of 950
REJ09B0079-0200