SH7710 Datasheet, PDF (531/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority: Even if channel 1 is performing burst-mode transfer in priority
fixed mode (CH0 > CH1), channel 0 starts transfer immediately when a request is made for
transfer on channel 0 with higher priority.
If channel 0 is also in burst mode at this time, channel 1 resumes transfer after transfer on channel
0 with higher priority is completed.
If channel 0 is in cycle-steal mode, channel 0 with higher priority transfers one transfer unit then
allows channel 1 to perform transfers without releasing bus mastership. Next, transfers are
performed alternately by channel 0, channel 1, channel 0, channel 1, and so on. This means that a
bus state is set for the CPU cycle after completion of the cycle-steal mode transfer is replaced with
the burst-mode transfer. (This operation is hereinafter referred to as burst-mode priority
execution.) Figure 13.11 shows an example.
If multiple channels are conflicting in burst mode, the channel with the highest priority is selected
for execution.
If multiple channels perform DMA transfers, bus mastership is not released to the bus master until
all conflicting burst transfers are completed.
CPU
DMA
CH1
DMA
CH1
DMA
CH0
CH0
DMA
CH1
CH1
DMA
CH0
CH0
DMA
CH1
DMA
CH1
CPU
CPU
DMAC CH1
Burst mode
Cycle-steal mode in
DMAC CH0 and CH1
DMAC CH1
Burst mode
CPU
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Figure 13.11 Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes according to the specification shown in figure 13.11.
However, no mixture of channels in cycle-steal mode and channels in burst mode is allowed.
13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 12, Bus State Controller (BSC).
Rev. 2.00 Dec. 07, 2005 Page 489 of 950
REJ09B0079-0200