SH7710 Datasheet, PDF (649/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.9 SIOF Interrupt Enable Register (SIIER)
SIIER is a used to enable the issue of SIOF interrupts. When each of the bits of this register is set
to 1, and the corresponding bit of the SISTR is set to 1, the SIOF issues an interrupt. SIIER is
initialized by a power-on reset or software reset.
Initial
Bit Bit Name Value R/W
15 
0
R
14 TCRDYE 0
R/W
13 TFEMPE 0
R/W
12 TDREQE 0
R/W
11 
0
R
10 RCRDYE 0
R/W
9
RFFULE 0
R/W
Description
Reserved
This bit is always read as 0. The write value should always
be 0.
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
(control interrupt)
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty (control
interrupt)
Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer requests
1: Enables interrupts due to transmit data transfer requests
(transmit interrupt)
Reserved
This bit is always read as 0. The write value should always
be 0.
Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
(control interrupt)
Receive FIFO Full Enable
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full (control
interrupt)
Rev. 2.00 Dec. 07, 2005 Page 607 of 950
REJ09B0079-0200