SH7710 Datasheet, PDF (517/996 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are
also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0.
Rev. 2.00 Dec. 07, 2005 Page 475 of 950
REJ09B0079-0200